首页|Design of Hybrid CMOS-Memristor Combinational Circuits: Maximizing Efficiency with Low Power, Area, and Delay
Design of Hybrid CMOS-Memristor Combinational Circuits: Maximizing Efficiency with Low Power, Area, and Delay
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NETL
NSTL
Springer Nature
In recent years, memristors have gathered significant attention as emerging electronic components due to their exceptional memory and switching capabilities, alongside attributes such as low power consumption, nano-scale dimensions, high endurance, retention, and compatibility with existing CMOS integrated circuits. These features made memristors as promising candidates for various applications in electronic circuits and chip designs, particularly in the realm of combinational circuits. In this article, we propose a novel XOR gate based on the principles of Memristor Ratioed Logic. The proposed XOR gate uses just two transistors and four memristors, a least count of devices with minimal power, delay, and area compared with the other Hybrid CMOS-Memristor logic designs. This design is extended to a 1-bit numeric comparator and full adder. PVT analysis is performed to ensure the reliability. Our findings suggest that the circuit presented offers improvements in power consumption, propagation delay, and integration density compared to alternative designs. These advancements highlight the potential of memristor-based logic circuits for enhancing the efficiency and performance of electronic systems.
NETL
NSTL
Springer Nature
