查看更多>>摘要:With increasing attention drawn to medical devices, analog-to-digital converters (ADCs) with higher resolutions are in great demand to address more complex signal processing needs. A second-order noise-shaping successive approximation register (NS-SAR) ADC with new approaches is presented in this paper. The area and power consumption of the integrator is reduced by reusing the operational amplifier. Correlated level shifting (CLS) is implemented to further boost the DC gain of the op-amp and alleviate the integral leakage, which can help to realize a sharp noise transfer function (NTF). Moreover, CLS suppresses the memory effect caused by the op-amp reuse strategy with higher gain of the op-amp. By combining Mismatch Error Shaping (MES) and Random Rotation-Based binary-weighted Selection (RRBS) techniques, the impact of capacitor mismatch on DAC is mitigated with little additional hardware cost and logic complexity. A prototype ADC is simulated in 180 nm CMOS technology and achieves an SNDR of 91.4 dB over a bandwidth of 31.25 kHz while consuming only 138 μW. Schreier figure-of-merit (FoMs) is 174.9 dB.
查看更多>>摘要:The analysis of signal transmission in Very Large Scale Integrated (VLSI) circuit, begins with a LC/RLC interconnect line representation which is lossless and low frequency interconnection. The transmission of signal of high frequency through interconnect networks can be modelled as a distributed RLCG transmission line interconnections. In this work delay and voltage models for RLCG type transmission lines are obtained by using single and two pole methodology using the concept of the first two moments of the transfer function of RLCG interconnects. In the proposed models, the closed form formulas are derived theoretically for the analytical delay, single pole delay and two-pole delay. Proposed single pole delay model and two-pole delay models' estimations are within 2.8% and 2.1% of SPICE delay estimation. The proposed approaches for various voltage and delay models have advantages in accuracy, novelty and minimum time required for simulation over the other existing models.
查看更多>>摘要:In recent years, memristors have gathered significant attention as emerging electronic components due to their exceptional memory and switching capabilities, alongside attributes such as low power consumption, nano-scale dimensions, high endurance, retention, and compatibility with existing CMOS integrated circuits. These features made memristors as promising candidates for various applications in electronic circuits and chip designs, particularly in the realm of combinational circuits. In this article, we propose a novel XOR gate based on the principles of Memristor Ratioed Logic. The proposed XOR gate uses just two transistors and four memristors, a least count of devices with minimal power, delay, and area compared with the other Hybrid CMOS-Memristor logic designs. This design is extended to a 1-bit numeric comparator and full adder. PVT analysis is performed to ensure the reliability. Our findings suggest that the circuit presented offers improvements in power consumption, propagation delay, and integration density compared to alternative designs. These advancements highlight the potential of memristor-based logic circuits for enhancing the efficiency and performance of electronic systems.
查看更多>>摘要:This research proposes a novel design for a current feedback instrumentation amplifier (CFIA) with a high common mode rejection ratio (CMRR) and programmable gain for diverse applications, including industrial, biomedical, and space systems. The parameters essential for achieving optimal performance are validated by simulating the circuit using 180 nm CMOS technology. The design of the proposed CFIA is implemented using an active block of bandwidth and transconductance enhanced folded cascode operational amplifier (BTE-FC), and a common mode feedback circuit. The proposed CFIA structure exhibits a differential gain that can be adjusted within the range of 0 to 60 dB, while its CMRR is 154.419 dB with a power dissipation of circuit is 2.43 mW and its cross-sectional area of 167.03 μm × 185 μm. The temperature range of the designed instrumentation amplifier is -40-125 ℃. The proposed design's robustness has been evaluated through Process, Voltage, and Temperature analysis alongside post-layout simulations. The effectiveness of the proposed design has been showcased through a comparative analysis with existing literature. The design proposed in this article demonstrates a high precision CMOS instrumentation amplifier with tunable gain and high CMRR, that is applicable in various domains, including space applications such as spacecraft instrumentation, environmental monitoring in space missions, and precise data acquisition for spaceborne scientific research. The inclusion of space applications underscores the amplifier's robustness and reliability in harsh environments, making it suitable for both terrestrial and extraterrestrial use.
查看更多>>摘要:Analog circuit soft fault diagnosis is an important method to ensure the continuous and stable operation of electronic systems, which directly affects the maintenance cost of the system. To improve the accuracy of soft fault diagnosis in analog circuits, this paper proposes a new diagnostic method. The method utilizes stationary wavelet transform to decompose the output response of analog circuits, obtaining their approximate coefficients and detail coefficients. Expectation maximization principal component analysis is used to reduce the dimensionality of detail coefficients, extracting essential information from high-frequency details, and simplifying data complexity. Then, the approximation coefficients are decomposed, and the aforementioned process is repeated. Finally, the deepest approximation coefficient is combined with all high-frequency information and inputted into the light gradient boosting machine for feature extraction and fault classification. This paper uses this method to test and analyze the soft fault diagnosis of the Sallen-Key band-pass filter circuit, Four-op-amp biquad high-pass filter circuit, and Leap-frog low-pass filter circuit. The experimental results show that the method proposed in this paper has high diagnostic accuracy and good noise interference tolerance. When the deviation between the component value and the nominal value is 30%, both the Sallen-Key band-pass filter circuit and the Four-op-amp biquad high-pass filter circuit can achieve a 100% diagnostic rate. Moreover, the diagnostic accuracy of the Leap-frog low-pass filtering circuit exceeds 98.89%.
查看更多>>摘要:A signal reshaping method based-on the application of low-pass (LP) type negative group delay (NGD) of a resistive-inductive (RL) circuit is developed in this article. To enhance comprehension of the LP-NGD design, an analytical theory of the RL-network topology considered for the signal reshaping is developed using voltage transfer function exploration. The main NGD characteristics, such as time-advance, NGD value and NGD cut-off frequency are defined. Design equations for calculating resistors and inductors that constitute the RL topology are formulated based on the targeted time-advance. After printed circuit boards (PCB) designed from an expected -0.5 ms time advance, two proofs-of-concept (PoC) dedicated to two test signals are examined to validate the NGD application method. Time-domain simulations and measurements, which closely match with a 38 ms duration pulse signal, confirm the developed signal reshaping method's feasibility by improving the input-output signal fidelity assessed with correlation coefficient from 57 to 99%. For arbitrary waveform one, it is improved from 32.5 to 99%. The signal reshaping NGD method is particularly useful for improving electronic circuit board and sensor performances through signal integrity enhancement.
查看更多>>摘要:Memristor emulators are of great importance in the investigation of nonlinearity and memory characteristics of memristors. Currently, most of the existing memristor emulators are active structures. In contrast, there has been a paucity of research conducted on emulators based on passive structures. This paper presents a novel approach based on unidirectional diode conductivity and complementary metal-oxide semiconductor (CMOS) transmission gates. The proposed method illustrates the potential for efficient operation in floating mode, offering a promising solution to the current limitations of passive memristor emulators. The new emulator circuit is symmetrical in that the input signal cross-activates the inverter to charge and discharge the capacitor and drive the transmission gate with the capacitor voltage. The circuit exhibits no DC bias and attains zero static power consumption in the absence of input excitation. Experimental implementation of a new memristor emulator circuit using SMIC 130nm CMOS pro-cess. The obtained results show that significant hysteresis curves can be maintained at input frequencies up to 300 MHz. The results of the theoretical analysis and simulation are corroborated by the layout design and post-simulation in Cadence, as well as by the physical circuit verification using commercial components on a breadboard. Logic gates and sequential logic circuits designed based on a new memristor emulator verify the practicality.
查看更多>>摘要:This paper studies dissipative control and filtering for a two-dimensional (2-D) nonlinear switched system with polytopic uncertainties and time-varying delays described by the Fornasini-Marchesini (FM) model. The nonlinearities are decomposed into linear forms under the Takagi-Sugeno (T-S) fuzzy rules. Assuming that uncertain parameters belong to a convex, bounded polyhedral domain, a parameter-dependent multiple Lyapunov-Krasovskii functional (MLKF) is established. Additionally, some free-weighting matrices that depend on the switching signal are introduced. This provides a new sufficient condition that exhibits reduced conservatism for the robust dissipative performance analysis of 2-D nonlinear polytopic uncertain switched systems. Furthermore, the design of parameter-independent and parameter-dependent state feedback controllers and filters for the system is investigated based on the proposed sufficient condition. Finally, three numerical examples are provided to validate our methods and demonstrate the reduced conservatism of our approach.
查看更多>>摘要:In this paper, the problem of state feedback quantized controller design for nonlinear networked cascade control system under multi-channel adaptive event-triggered strategy is studied. Based on the Takagi-Sugeno fuzzy model, the nonlinear system is modeled. An improved adaptive event-triggered mechanism is proposed, in which the dynamic threshold function is composed of multiple dynamic sub-functions, and the sampling data and trigger data of the sensor-controller are fully considered, which significantly alleviates the network burden of the communication channel. In addition, the dynamic quantization parameters of the dynamic quantizer are improved. The dynamic quantization parameters are coordinated by the quantized signal and the original parameters, which ensures that there is no singularity problem in the dynamic quantization parameters. Finally, the effectiveness and superiority of the proposed design method are verified by simulation examples.
查看更多>>摘要:This study addresses the controllability of second-order signed multi-agent networks based on matrix weights. Some controllability conditions of signed second-order multi-agent networks under matrix-weighted topology for the heterogeneous networks and homogenous networks are built, respectively. In addition, the second-order controllability of signed networks with matrix-weights under structurally balanced conditions is considered with selecting appropriate leaders. Finally, simulations and examples are provided to demonstrate the theoretical results.