首页|A Low Power Noise-Shaping SAR ADC with Improved Integrator and Hybrid OAC Mismatch Mitigation Technique
A Low Power Noise-Shaping SAR ADC with Improved Integrator and Hybrid OAC Mismatch Mitigation Technique
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NETL
NSTL
Springer Nature
With increasing attention drawn to medical devices, analog-to-digital converters (ADCs) with higher resolutions are in great demand to address more complex signal processing needs. A second-order noise-shaping successive approximation register (NS-SAR) ADC with new approaches is presented in this paper. The area and power consumption of the integrator is reduced by reusing the operational amplifier. Correlated level shifting (CLS) is implemented to further boost the DC gain of the op-amp and alleviate the integral leakage, which can help to realize a sharp noise transfer function (NTF). Moreover, CLS suppresses the memory effect caused by the op-amp reuse strategy with higher gain of the op-amp. By combining Mismatch Error Shaping (MES) and Random Rotation-Based binary-weighted Selection (RRBS) techniques, the impact of capacitor mismatch on DAC is mitigated with little additional hardware cost and logic complexity. A prototype ADC is simulated in 180 nm CMOS technology and achieves an SNDR of 91.4 dB over a bandwidth of 31.25 kHz while consuming only 138 μW. Schreier figure-of-merit (FoMs) is 174.9 dB.
Noise-shaping SAR ADCCorrelated level shiftingIntegratorDAC mismatch mitigationMismatch error shaping
Gang Jin、Haofeng Wang、Kexin Zhang、Hualian Tang
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Faculty of Integrated Circuit, Xidian University, Xi an 710071, People's Republic of China
NETL
NSTL
Springer Nature
