查看更多>>摘要：The integrated sensing and communications(ISAC)technology has been perceived as a key feature of 5G-Advanced and beyond mobile communication networks.Compared with sensing in millimeter-wave bands,sensing at sub-6 GHz band is an exceptional incentive to promote the industrialization process of ISAC due to its incomparable advantages in industrial development,especially for intelligent transportation and smart drone networks.This paper elaborates on the top challenges of sub-6 GHz ISAC technologies,as well as the potential solutions to improve the sensing capability.
查看更多>>摘要：A novel trench insulated gate bipolar transistor(TIGBT)with a shallow emitter trench controlled P-type dummy region(STCP-TIGBT)is proposed.Compared with the conventional TIGBT with floating P-type dummy region(CFP-TIGBT)and TIGBT with floating P-type dummy region and normally on hole path(HFP-TIGBT),the proposed STCP structure not only speeds up the extraction of excessive holes in the turn-off process but also reduces the Miller plateau charge(Qgc).Therefore,both the power loss and electromagnetic interference(EMI)noise are significantly reduced.Simulation results show that the Qgc of the proposed device is only 501 nC/cm2,which is reduced by 58.5％and 26.4％when compared to the CFP-TIGBT and HFP-TIGBT,respectively.At same on-state voltage drop(Vceon)of 1.02 V,the turn-off loss(Eoff)of the proposed device is 13.49 mJ/cm2,which is 64.6％and 67.6％less than those of the CFP-TIGBT and HFP-TIGBT,respectively.Moreover,the reverse recovery dVak/dt of the freewheeling diode at same turn-on loss(Eon)of 31.8 mJ/cm2 for the proposed STCP-TIGBT is only 2.15 kV/μs,which is reduced by 91.3％and 57.2％when compared to 24.69 kV/μs and 5.02 kV/μs for the CFP-TIGBT and HFP-TIGBT,respectively.The reduced dV/dt significantly suppresses the electromagnetic interference noise generated by the proposed device.
查看更多>>摘要：Recent popularity to realize image recognition by memristor-based neural network hardware systems has been witnessed owing to their similarities to neurons and synapses.However,the stochastic formation of conductive filaments inside the oxide memristor devices inevitably makes them face some drawbacks,represented by relatively higher power consumption and severer resistance switching variability.In thiswork,we design and fabricate the Ag/MXene(Ti3C2)/SiO2/Pt memristor after considering the stronger interactions between Ti3C2 and Ag ions,which lead to a Ti3C2/SiO2 structure memristor owning to much lower"SET"voltage and smaller resistance switching fluctuation than pure SiO2 memristor.Furthermore,the conductances of the Ag/Ti3C2/SiO2/Pt memristor have been modulated by changing the number of the applied programming pulse,and two typical biological behaviors,i.e.,long-term potentiation and long-term depression,have been achieved.Finally,device conductances are introduced into an integrated device-to-algorithm framework as synaptic weights,by which the MNIST hand-written digits are recog-nized with accuracy up to 77.39％.
查看更多>>摘要：Flexible printed circuit(FPC)design in complex scenarios has a list of pin concentration areas,which lead to extremely congested intersection regions while connecting the pins.Currently,it is challenging to explore the routability and to find topologically non-crossing and routable paths manually for the nets timely.The existing bus planning methods cannot offer optimal solutions concerning the special resource distribution of the FPC design.To investigate an effective way to shorten the routing time of FPC and achieve enhanced performance,a bus planning algorithm is proposed to tackle complex area connection problems.On the basis of the pin location information,the routing space is partitioned and generally represented as an undirected graph,and the topological non-crossing rela-tionship between different regions is obtained using the dynamic pin sequence.Considering the routability and elec-trical constraints,a heuristic algorithm is proposed to search the optimal location of the crossing point on the region boundary.Experimental results on industrial cases show that the proposed algorithm realize better performance in terms of count and routability in comparison with numerous selected state-of-the-art router and methods.
查看更多>>摘要：A radiation-hardened phase-locked loop is proposed for phase interpolator clock and data recovery purposes.A sensitive node-compressed charge pump and multi-node cross coupling voltage-controlled oscillators are proposed in this phase-locked loop with the goal of achieving good jitter performance and improving anti-SET(SET,single-event transient)capability.The root mean square(RMS)jitter of the phase-locked loop is reduced from 3.7 ps to 2.58 ps at 2 GHz,while the laser threshold is improved from 120 pJ to 370 pJ compared to the unhardened phase-locked loop.The hardened phase-locked loop also does not lose its lock state from linear energy transfers(LETs)of 3.3 to 37.3 MeV·cm2/mg.
查看更多>>摘要：To solve the problems of redundant logic resources and poor scalability in protocol controller circuits among communication networks,we propose a traffic-driven software defined interconnection(TSDI)mechanism.The unified software defined interconnection interface standards and the normalized interconnection topology are designed to implement the architecture of TSDI-based protocol controller.The key indicators of power,performance and area(PPA)can be realized while resolving the flexible interconnection of the controller.We designed a TSDI-based RapidIO controller as an example.Compared to traditional designs,the design could achieve more protocol scalability,and RapidIO protocol standards of Gen4 could be supported directly.The key PPA indicators,such as a lower delay of 56.1 ns and more than twice throughput of 98.1 Gbps,were achieved at the cost of a 23.4％area increase.
查看更多>>摘要：Silicon physical unclonable function(PUF)implemented by static random access memory(SRAM)exists inherent demerit of unstable cells due to noise of environment and circuits,which significantly restricts its re-producibility.In this paper,a 16T SRAM cell with reset-delay circuit and a 2-stage voltage ramp up is fabricated and reported.Compared to conventional SRAM structure,each PUF cell adds a pair of pull-up PMOS(P-channel metal oxide semiconductor)and pull-down NMOS(N-channel metal oxide semiconductor)controlled by reset and delayed-reset signals respectively,resulting in two positive feedback stages with different amplification coefficients when the voltage is ramped up.PUF array consists of 4064 cells,322 dummy cells and a group of 8 series-connected inverters with an area of 304 μm × 650 μm to match the digital post-processing module.PUF test chip was fabricated in HH-Grace 110 nm platform with total area 1140 × 1140 μm2.The average HDintra(intra-chip Hamming distance,also bit error rate,BER)and HDinter(inter-chip Hamming distance)values of the 50 PUF chips in SOP16 package mea-sured at normal point(1.5 V/25 ℃)were 1.92％and 49.85％,respectively.
查看更多>>摘要：Wideband high power amplifier(PA)with poor harmonic suppression will degrade the performance of the active electronically scanned array(AESA)due to its harmonic products falling into the operating bandwidth of a wideband T/R module.In view of this,a compact reconfigurable harmonic suppress circuit(HSC)is proposed to achieve low in-band harmonic for compact T/R module with multiple octaves under TX-mode operation.The HSC consists of eight microstrip resonant stubs with high impedance and multiple p-i-n switches.By controlling the p-i-n switches,the HSC can work in three states.When six of the used p-i-n switches are"ON"state,the corresponding microstrip resonant stubs are loaded onto the 50 Ω transmission line,which performs a bandstop filter(BSF).For verification,the HSC with bandwidth of 12-15 GHz/15-18 GHz is designed to apply to a 6-18 GHz T/R module.As a result,the second harmonic of 6-9 GHz transmitting signal can be suppressed below 32 dBc when compared to the PA's fundamental output.While the p-i-n switches are"OFF"state,the HSC is almost the same as a 50 Ω trans-mission line,which will have a little effect on the 9-18 GHz transmitting signal.The measurement results approxi-mately agree with the calculated results and simulated results,which demonstrate the validity of the proposed HSC.
查看更多>>摘要：Since many third parties involved in integrated circuit(IC)manufacturing,hardware Trojans mali-cious implantation have become a threat to the IC industry.Therefore,varieties of reliable hardware Trojan detection methods are needed.Since electromagnetic radiation is an inherent phenomenon of electronic devices,there are signif-icant differences in the electromagnetic radiated characteristics for circuits with different structures and operating states.In this paper,a novel hardware Trojan detection method is proposed,which considers the electromagnetic radiation differences caused by hardware Trojan implantation.Experiments of detecting hardware Trojan in field programmable gate arrays show that the proposed method can effectively distinguish the ICs with Trojan from the ones without Trojan by the radiated emission.
查看更多>>摘要：A high dynamic range and low-noise CMOS(complementary metal-oxide-semiconductor transistor)front-end interface integrated circuit(IC)with multi-channel detection is presented in this paper.Two different current detection channels,composed of a trans-impedance amplifier(TIA)and an integrator-differentiator TIA,are used to boost the current detection range.A capacitance-coupled instrument amplifier(CCIA)is also included to realize high precision voltage detection.A fourth-order sigma-delta modulator using a second-order loop filter and a second-order noise shaping integral quantizer is adopted to realize effective number of bits above 16 bits.The presented interface IC is implemented in 0.18-μm CMOS process with supply voltage of 3.3 V,and a proto-type electrochemical sensor platform with miniaturized sensor array is developed to verify the functionality of the interface IC.Measurement results indicate that the designed interface IC achieves 157.8 dB current detection dynamic range,and the measured input-referred current noise and voltage noise floor are 1.04 pA and 58.4 nV within 10 kHz integration bandwidths,respectively.
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