查看更多>>摘要：In this article, the influence of Forming Gas Annealing (FGA) on the Positive Bias Temperature Instability (PBTI) characteristics of n-vertical C-shaped-channel nanosheet FET (n-VCNFET) is studied. The experimental results show that the extra FGA can significantly suppress both the initial and generated interface traps in PBTI. Moreover, in ultra-fast PBTI the pre-existing trap and total trap of VCNFET due to FGA decreases by 35 % and 31 %, respectively. The energy level of the oxide trap under PBTI and recovery doesn't change, in other words, the FGA induces the oxide trap density of the devices to decrease by 36 % at 125 degrees C and 1.4 V VOV. The optimization effect of FGA annealing has been further confirmed from the perspective of trap generation. It provides a guideline for the PBTI improvement of VCNFET in trap scopes.
查看更多>>摘要：In this paper we present simulation based radiation damage modeling of 4H silicon carbide (SiC) using the technology computer aided design (TCAD) tools for up to 1 kV forward and backward bias. After verifying the TCAD framework from Global TCAD Solutions (GTS) against Sentaurus simulations for silicon we use it to approximate measurements of neutron-irradiated 4H-SiC particle detectors, i.e., pin-diodes. Based on our simulations we are not only able to evaluate the accuracy of the predictions but also to provide an explanation for the almost negligible current of radiated devices under high forward bias.
查看更多>>摘要：Strain engineering is a common approach for enhancing the mobility of semiconductor materials and improving the performance of conventional and novel transistors. Understanding the strain distribution is important for optimizing device characteristics. Transmission electron microscopy (TEM) is a crucial technique for evaluating strain at the nanoscale. However, due to the ongoing reduction in electronic device dimensions, assessing strain via TEM has become increasingly challenging. Many different techniques have been developed in recent years with the aim of analysing complex structures. In this work, we investigate the capabilities of the recently developed Bessel beam electron diffraction (BBED) method to evaluate strain by TEM in fully processed fin-field effect transistor (FinFET) devices and in cutting edge nano-sheet complementary-FET (NS-CFET) technology. TEM analysis of fully processed devices is challenging due to the presence of artefacts generated by different materials and multiple structures overlapping in projection in TEM images. We demonstrate the capability of the BBED technique to reveal strain in fully processed FinFET while exploring the dependence of strain on layout variations. NS-CFETs are an attractive device architecture for beyond 1 nm logic technology nodes. Strain distribution in these devices is more complex than in FinFETs due to the presence of very thin layers and reduced channel dimensions. We compare the BBED method with the well-known techniques of nano-beam electron diffraction (NBED) and geometric phase analysis (GPA) for analysing strain in these structures. The BBED technique, despite a simple experimental setup, shows good accuracy and spatial resolution, being able to resolve interlayers thinner than 2 nm. Compared to NBED and GPA, the BBED technique offers better performance and is therefore a promising method to study strain in future transistor devices.
查看更多>>摘要：With the advent of FinFET technology, especially in the application of 14 nm and above nodes, the front-end-of-line (FEOL) defects at the transistor level have become increasingly significant. These minute FEOL defects have a critical impact on the yield and reliability of the ultimate chipset. This paper focuses on two types of FEOL defects identified in 14 nm FinFET technology. The research shows that both of these FEOL defects can lead to leakage in MOSFETs. We have conducted an in-depth analysis of the distinct failure mechanisms of these two defects and their potential formation causes. It is expected to help wafer factories achieve effective improvements. The study indicates that these two failure modes might be triggered by oxide defects in different steps of the FEOL process flow. Specifically, in one case, dielectric breakdown-induced epitaxy (DBIE) causes NMOS gate leakage, which might be ascribed to the presence of defects in the bottom interface layer (BIL) of the oxide. In another instance, PMOS leakage caused by germanium bridge defects might result from oxide defects as the etch stop layer (ESL) and the influence of subsequent process steps on the defects. This research provides an essential guiding direction for wafer factories to optimize the manufacturing process of 14 nm FinFET products and improve yield and quality. At the same time, this study also offers a valuable reference basis for the failure analysis of FinFET devices.
查看更多>>摘要：During the scaling down of hybrid bonding pairs, controllable misalignment is particularly important for ensuring remarkable electrical performance. This article presents the finite element modeling methodology to preview the significance of misalignment on resistance and capacitance values. Design parameters such as the via array, pad size, shape, and asymmetric structure are comprehensively considered. The results show that the electrical properties of interconnects at the small pitch is more sensitive to misalignment. The via array affects the current distribution serving as the inter-metal connection channel. The size and shape of the pad directly determine the effective contact area and effective space under various misalignment. The alignment error redundancy provided by the asymmetric structure is an option to alleviate the problem. This work contributes to understanding the impact weight of misalignment on electrical performance under different design conditions and formulating appropriate alignment rules.
查看更多>>摘要：The recent discovery of two-dimensional ferroelectric semiconductors, such as In2Se3, has opened promising avenues for ultra-thin micro-nano electronic devices, and energy-efficient neuromorphic systems. Despite these exciting prospects, achieving large-area, high-quality, layer-controlled growth of single-phase In2Se3 remains a considerable challenge. In this study, we present a seed-assisted strategy for growing uniform, centimeter-scale (3'-In2Se3 thin films by mixing In2O3 and In2Se3 single crystals in a specific ratio. The resulting (3'-In2Se3 phase and composition are verified through X-ray diffraction, transmission electron microscopy, and Raman spectroscopy. Furthermore, the ferroelectric properties and domain configurations have been characterized by using polarized light microscopy and piezoresponse force microscopy. Importantly, we investigate the topological evolution of ferroelectric domains across films with varying thicknesses, revealing insights into domain structure modulation. This growth method not only provides a scalable route for synthesizing similar ferroelectric twodimensional materials but also a possibility for the practical integration of (3'-In2Se3 in optoelectronic, neuromorphic, and other advanced micro-nano electronic applications.
查看更多>>摘要：In this research article, we propose a tunable floating-type memristor emulator circuit with long-term memory (LTM) capabilities. The overall circuit consists of a Voltage Differential Transconductance Amplifier (VDTA), a Voltage Differential Complementary Amplifier (VDCA), and other basic components. The proposed emulator effectively prevents charge leakage on the capacitor by incorporating a switching circuit, thereby achieving longterm memory functionality. The emulator operates stably at a frequency of 10 MHz and supports seamless switching between incremental and decremental modes by altering the polarity of the input voltage. Moreover, the emulator exhibits excellent tunability, allowing adjustments to the equivalent memristor model by modifying the bias voltage and the aspect ratio of MOS transistors. The proposed emulator has been laid out and simulated using TSMC 0.18 mu m process parameters in the Cadence Virtuoso platform. The simulation results align perfectly with the design and analysis, confirming the feasibility of the circuit. Finally, we explore potential applications of the proposed emulator in read-write circuit and memristor array circuit.
查看更多>>摘要：The relentless miniaturization of critical feature sizes in integrated circuits has set increasingly stringent demands on the precision of via etching processes. Current research predominantly focuses on the development of gases and optimization of processes. However, the role of etching gas purity and the impact of gas impurities have not yet been the subject of dedicated studies. Here, the etching behavior of silicon dioxide using two different purities of etching gases is investigated, examining the etching rate and morphology of SiO2 films under identical etching parameters. Compared to 99.999 % purity, the 99.99999 % purity C4F8 gas achieves a more stable and uniform etching rate with sidewall angles of 86.6 degrees (closer to a 90 degrees angle). This is primarily attributed to the reduction of etch-active impurities in the C4F8 gas, which decreases etching variability and minimizes damage to the sidewall fluorocarbon protective layer. Our research provides theoretical and experimental support for the advancement of subsequent etching simulation studies and the application of high-purity etching gases.
查看更多>>摘要：Wearable health monitoring systems have gained significant attention for real-time physiological signal tracking, particularly in elderly care settings where continuous, non-invasive monitoring is critical. Current systems, however, face limitations in multi-signal integration, user comfort, and practicality for long-term use. Existing approaches often rely on separate devices for measuring vital signs, leading to cumbersome setups and restricted mobility. Additionally, few solutions support simultaneous multi-user monitoring, hindering scalability in group care environments like nursing homes. In this study, we present a highly integrated waistband device that addresses these gaps by concurrently measuring respiration, electrocardiogram (ECG), and body temperature. The respiratory sensor employs a resistive pressure sensor. Its alignment with the ECG electrodes and the temperature sensor eliminates the need for auxiliary respiratory devices (e.g., masks) and enhances wearability. With the integration of a Bluetooth transmission circuit system, this real-time health monitoring system enables long-term stable testing for multiple users. A 24-h synchronized test involving 10 participants was conducted, demonstrating effective health monitoring capabilities and the potential to identify underlying health issues. This innovation provides a scalable, comfortable solution for intelligent healthcare systems, demonstrating practical value in elderly care applications.
查看更多>>摘要：This work investigates the impact of the device technological parameter - gate-drain access region spacing (LGD) for GaN High Electron Mobility Transistors (HEMTs), on the design of low noise amplifiers (LNAs) for the 3-4 GHz range. We compare two GaN LNA variants, characterized by LGD values of 0.875 mu m and 1 mu m, to highlight the significance of gate-drain spacings in determining performance metrics. This study contributes insights into the effect of gate-drain spacing on the GaN LNAs, and evaluates the RF characteristics, Noise Fig. (NF), and power metrics for different LGD values. Based on our findings, we assert that the 0.875 mu m LGD LNA exhibits superior performance over its counterpart in the evaluated benchmarks, along with the physical reasoning.
NETL
NSTL
Elsevier